1. Field of the Invention
The invention relates to a fabrication method for an isolation structure of a semiconductor device, and more particularly to a fabrication method for a deep trench isolation structure of a high-voltage device.
2. Description of the Related Art
Recently, as the manufacturing techniques of semiconductor integrated circuits develop, the request of highly integrating controllers, memories, low-voltage operating circuits and high-voltage power devices on a single chip increases to achieve a single-chip system, in which the power device including vertical double-diffused transistor (VDMOS), lateral double-diffused transistor (LDMOS) and insulated gate bipolar transistor (IGBT), is used to increase power transform efficiency and decrease energy wastage. Since the high-voltage transistor and the low-voltage CMOS circuit device are provided on the single chip, an isolation structure is required to isolate the high-voltage device and the low-voltage device. Also, in order to fit in with a high breakdown voltage that is requested by the high-voltage device, the isolation structure must reach predetermined-depth isolation. Therefore, a deep trench isolation structure formed in a thick epitaxial layer has been developed by extra providing an epitaxial layer on a semiconductor substrate.
FIG. 1 is a cross-section of a conventional isolation structure of a high-voltage device. In a case of a P-type semiconductor silicon substrate 10, an N-type epitaxial layer 12 is provided on the P-type semiconductor silicon substrate 10, and an N-type buried layer (NBL) 14 is embedded between the N-type epitaxial layer 12 and the P-type semiconductor silicon substrate 10. Also, two P+-type deep trench isolation structures 16 are formed in the N-type epitaxial layer 12 to define a high-voltage area, and a plurality of field oxidation (FOX) regions 18 are formed on the upper surface of the N-type epitaxial layer 12 to isolate components within the high-voltage area. An N+-type sinker 20 is formed in the N-type epitaxial layer 12 between the first FOX region 18I and the second FOX region 18II, and electrically connected to exterior wires formed overlying the N-type epitaxial layer 12. Moreover, a P-type body 22 is formed in the N-type epitaxial layer 12 between the second FOX region 18II and the third FOX region 18III, and a pair of N+-type diffusion regions 24 and a pair of P+-type diffusion regions 26 that are respectively electrically connected to exterior wires are formed in the P-type body 22. Furthermore, a gate structure 28 is formed on the surface of the P-type body 22.
In manufacturing the P+-type deep trench isolation structure 16, a deep trench formed in the N-type epitaxial layer 12 is filled with an oxide layer, and then ion implantation is employed to implant B+ ions into the oxide layer by, and finally thermal annealing is employed to diffuse the B+ ions in the oxide layer. For spreading the B+ ions around within the deep trench, however, the procedure time of the thermal annealing is very long, resulting in increased thermal budget. Also, since the thermal annealing makes the B+ ions diffuse both toward a vertical direction and a lateral direction, the width W of the P+-type deep trench isolation structure 16 increases as the depth H of the P+-type deep trench isolation structure 16 increases. When the deep trench 16 is requested to reach predetermined-depth isolation, the lateral size of the P+-type deep trench isolation structure is also increases, resulting in the required size of a chip being increased.
Accordingly, how to forming a deep trench isolation structure with decreasing thermal budget and reducing the lateral size of the deep trench isolation structure to solve the problems caused by the prior method is called for.